DS3106LN+【PDF 5/92 页】IC TIMING LINE CARD 64-LQFP

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DS3106

Table 6-6. Power-Supply Pin Descriptions

PIN NAME

(1)

TYPE

(2)

PIN DESCRIPTION

VDD

Core Power Supply. 1.8V

±10%.

VDDIO

I/O Power Supply. 3.3V

±5%.

VSS

Ground Reference

AVDD_DL

Power Supply for OC6 Digital Logic. 1.8V

±10%.

AVSS_DL

Return for OC6 Digital Logic

VDD_OC6

Power Supply for Differential Output OC6POS/NEG. 1.8V

±10%.

VSS_OC6

Return for LVDS Differential Output OC6POS/NEG

AVDD_PLL1

Power Supply for Master Clock Generator APLL. 1.8V

±10%.

AVSS_PLL1

Return for Master Clock Generator APLL

AVDD_PLL2

Power Supply for T0 APLL. 1.8V

±10%.

AVSS_PLL2

Return for T0 APLL

AVDD_PLL3

Power Supply for T4 APLL. 1.8V

±10%.

AVSS_PLL3

Return for T4 APLL

AVDD_PLL4

Power Supply for T0 APLL2. 1.8V

±10%.

AVSS_PLL4

Return for T0 APLL2

Note 1: All pin names with an overbar (e.g.,

RST) are active low.

Note 2: All pins, except power and analog pins, are CMOS/TTL, unless otherwise specified in the pin description.

PIN TYPES

I = input pin

IDIFF = input pin that is LVDS/LVPECL differential signal compatible

IPD = input pin with internal 50k pulldown

IPU = input pin with internal 50k pullup

I/O = input/output pin

IOPD = input/output pin with internal 50k pulldown

IOPU = input/output pin with internal 50k pullup

O = output pin

O3 = output pin that can be placed in a high-impedance state

ODIFF = output pin that is LVDS/LVPECL differential signal compatible

P = power-supply pin

Note 3: All digital pins, except OCn, are I/O pins in JTAG mode. OCn pins do not have JTAG functionality.

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